1. Field of the Invention
This invention relates to methods for resolving problems caused by coupling effects between neighboring wires, and particularly to adjusting the effects of inductive coupling and/or capacitive coupling in bus lines.
2. Description of Background
Heretofore, in many cases busses in integrated circuits have been shifted a certain number of bits in the horizontal or vertical direction. This is commonly done in shifters, multipliers, and unit wiring. FIGS. 1A and 1B illustrate a common, i.e. normal, way people and tools wire provide the shifting of wiring FIG. 1A is a table illustrating the shifting of six wires in an array of busses between two stages of a prior art integrated circuit device. FIG. 1B illustrates a prior art example of the physical configuration of the busses of the table in FIG. 1A. The order for N wires in the vertical directions is 0,1,2,3, . . . , N−1, For N wires in the bus and a shift or throw of length L bits there are (L−1)*2 of bits of neighboring wire for each wire aside from the periphery of the lines in the bus.
From the point of view of the problems associated with coupling capacitance and noise, this is undesirable. Any given wire is completely surrounded by neighbors that are usually hostile, i.e. cross talk is created by induction, which degrades the signal to noise ratio and slows down signal propagation especially when common timing signals are employed thereon. For N wires in a bus and a shift or throw of length L bits there is (L−1)*2 bits of neighboring wire for each wire. This provides the maximum amount of coupling capacitance due to proximity of wires to each other. For example, consider a system with ten wires, shifting fourteen bits. This assumes that there is no freedom to space wires out and that the designer or tool has the exact amount of wiring tracks as wires.
U.S. Patent Application Publication No. 2006/0143586 of Suaya entitled “Synthesis Strategies Based on the Appropriate use of Inductance Effects” describes optimizing the signal propagation speed on a wiring layout.
U.S. Pat. No. 7,139,993 of Proebsting entitled “Method and Apparatus for Routing Differential Signals Across a Semiconductor Chip” provides an arrangement of pairs of wires carrying differential signals across a semiconductor chip with those pairs of wires organized within a set of parallel tracks on the chip.
U.S. Pat. No. 6,999,375 of Jung entitled “Synchronous Semiconductor Device And Method Of Preventing Coupling Between Data Buses” describes a synchronous semiconductor device and a method for preventing coupling between data buses.
U.S. Pat. No. 6,772,406 of Trimberger entitled “Method For Making Large-Scale ASIC Using Pre-Engineered Long Distance Routing Structure” describes optimal routing line segments and associated buffers.
U.S. Pat. No. 6,388,277 of Kobayashi entitled “Auto Placement and Routing Device and Semiconductor Integrated Circuit” provides an auto placement and routing device that lays out wiring with consideration for influences of an increase in an effective coupling capacitance.
U.S. Pat. No. 6,189,133 of Durham, which is assigned to IBM, entitled “Coupling Noise Reduction Technique Using Reset Timing” describes reducing false transitions resulting from capacitive coupling between parallel interconnects driven by dynamic circuits by classifying interconnects based on the timing of expected data transitions in the signals they carry.